Continuing refinements in semiconductor materials development and circuit design have made it possible to apply integrated circuit technology to a broader (higher frequency) range of signal processing problems, and thereby significantly reduce the size and cost of system components. One of the more recent approaches proposed for producing high frequency application, GaAs-resident systems and devices involves a fabrication technique that is application specific, similar to that used for implementing silicon wafer processing, wherein a variety of circuit building blocks (e.g. transistors, resistors, diodes) are formed in a semiconductor wafer and selectively interconnected and matched to realize an overall signal processing functionality (e.g. mixer, amplifier, switch, oscillator, limiter, isolator, attenuator), as well as an overall specification (i.e. operating frequency and power range).
More particularly, within a (GaAs) wafer, a plurality of elemental circuit components, such as diodes, field effect transistors, capacitors and resistors are strategically located to form a set of "footprints", the selective interconnection of which, by means of an overlying metallization pattern (which may also include additional passive components, such as inductors, transformers and capacitors), yields a `personalized` architecture that is dedicated to a specific signal processing application. Conventionally, the metallization pattern has been formed of two layers of metal, the shapes and locations of which relative to one another define the characteristics of reactance elements, such as inductors and capacitors, through which the wafer-resident "footprints" are personalized.
For this purpose, the first metal layer is normally selectively formed either directly on a conductive layer, such as an FET gate/ohmic contact layer, or on a wafer passivation layer and is itself passivated by an MIM dielectric layer. The second metallization layer is then formed as an air-bridge between selected portions of the first metallization layer. Where tuning elements, such as MIM capacitors, are incorporated into the metallization interconnect structure, the circuit properties of each element are dependent upon the geometry of each metallization layer, so that multiple masks must be prepared in order to `personalize` the footprint. In addition, fabrication complexity (which impacts circuit yield and cost) is increased because of the use of a complicated dielectric laminate structure and the consequential need for a dummy layer to achieve proper step coverage and prevent unwanted etch back (of the first metallization layer). As a result, what is supposed to be a circuit fabrication aid (the availability of a precursor footprint), in reality, only partially facilitates the implementation of a particular circuit design.